1. Field of the Invention
The present invention relates to a layout design technology of a semiconductor integrated circuit, and a semiconductor memory device of a CMOS SRAM (Static Random Access Memory, hereinafter referred to as “CMOS SRAM”).
2. Description of the Prior Art
With a rapid progress in a microfabrication of a semiconductor, a processing dimension of nearly 100 nm has begun to be achieved in recent years, while a lithography technology has increasingly become a bottleneck for the progress in microfabrication. Taking these situations into account, there has begun to be used a horizontal memory cell layout which is easy to be lithographically processed in stead of a vertical memory cell layout which has been mainly used formerly as a layout structure of an SRAM memory cell.
There is schematically shown a layout example of a lower layer section of a vertical memory cell of a conventional CMOS SRAM in FIG. 20. In FIG. 20, reference numeral 100 represents a P-well; 101, an N-well; 102, a boundary line between the wells; 103, a diffusion layer of a source or a drain (when on P-well 100, N type diffusion layer; on N-well 101, P type diffusion layer); 104, a gate electrode; 105, a contact hole of connecting the diffusion layer 103 or the gate electrode 104 to a first-layer metal interconnection (not shown); 107, an N-channel access transistor; 108, an N-channel drive transistor; 109, a P-channel load transistor; and 110, a cell boundary frame for 1 bit of the memory cell.
There is schematically shown a layout example of a lower layer section of a horizontal memory cell of a conventional CMOS SRAM in FIG. 21. In FIG. 21, the same reference numerals are given to portions corresponding or similar to those of FIG. 20; and reference numeral 106 represents a shared contact of connecting the diffusion layer 103 to the gate electrode 104 with the first-layer metal interconnection (not shown) by one contact hole. Both of FIG. 20 and FIG. 21 show a six-transistor type SRAM memory cell comprising a pair of the N-channel access transistors 107, a pair of the N-channel drive transistors 108, and a pair of the P-channel load transistors 109; and a circuit diagram of such a memory cell is shown by FIG. 28. In the case of the horizontal memory cell shown in FIG. 21, the boundary line 102 between the wells is extended in a vertical direction in FIG. 21.
This horizontal memory cell is generally arranged in flip as shown in FIG. 22. In FIG. 22, reference numeral 221 represents a memory cell array, and reference numeral 222 represents a horizontal memory cell.
Interconnection layouts of the horizontal memory cell are also shown in FIGS. 23 to 25. Layouts of the first-layer metal interconnection, the second-layer metal interconnection, and the third-layer metal interconnection are shown in FIG. 23, FIG. 24, and FIG. 25, respectively; and in FIG. 23, reference numeral 111 represents a first-layer interconnection. In FIG. 24, reference numerals 112, and 113 represent a second-layer interconnection, and a via hole section (connecting section by via hole) of connecting the first-layer interconnection 111 to the second-layer interconnection 112, respectively. Further, reference numeral 114 represents a positive bit line (BL in FIG. 28); 115, a negative bit line (/BL in FIG. 28); and 116, a VDD power supply interconnection; and these are formed with the second-layer interconnection 112. In FIG. 25, reference numeral 117 represents a third-layer interconnection, and reference numeral 118 represents a via section of connecting the second-layer interconnection 112 to the third-layer interconnection 117. Further, reference numeral 119 represents a word line (WL in FIG. 28); 120, a VSS power supply interconnection; and these are formed with the third-layer interconnection 117.
As can be seen when comparing a layout of the vertical memory cell of FIG. 20 with that of the horizontal memory cell of FIG. 21, in the horizontal memory cell, the diffusion layer 103 and the gate electrode 104 are straight in shape extended in the same direction, so that it has a layout to facilitate pattern formation, thereby providing a merit that a lithography process thereof would be performed further easily than that of the vertical memory cell. Further, since the cell shape provides a landscape shape, the bit line length extended in a vertical direction becomes shorter compared with that of the vertical memory cell, so that a bit line capacitance is reduced, and thereby also providing a merit that improvement in speed and reduction in power dissipation are advantageously achieved. Since a narrow gate width is used for the transistors within the memory cell for area reduction, and it will further have a configuration that a number of memory cells are connected to the bit line, a drive load of the memory cell is increased, so that a bit line drive time is one of the most important factors in access time improvement in speed.
Incidentally, in the example of the above horizontal memory cell, the description has been made of the example where the bit line has been formed with the second-layer interconnection (hereafter referred to as “second layer bit line type ”), and in addition to that, description will be made of an example where the bit line is formed with the third-layer interconnection (hereafter referred to as “third layer bit line type”). The layout of the lower layer section and the first-layer metal interconnection of the third-layer bit line type horizontal memory cell is similar to that of the lower layer section and the first-layer metal interconnection of the second layer bit line type horizontal memory cell shown in FIG. 21 and FIG. 23, respectively. A layout of the second-layer interconnection and a layout of the third-layer interconnection of the third layer bit line type horizontal memory cell are shown in FIG. 26 and FIG. 27, respectively. In this third layer bit line type, a word line 351 is formed with the second-layer interconnection 112 as shown in FIG. 26, and a positive bit line 352, a negative bit line 353, a VDD power supply interconnection 354, and a VSS power supply interconnection 355 are formed with the third-layer interconnection 117 as shown in FIG. 27.
A bit line capacitance to a substrate of the third layer bit line type becomes lower than that of the second layer bit line type. However, since many interconnection patterns exist in the second-layer interconnection, a capacitance difference to the substrate is hardly effective. Further, the via section depth of the third layer bit line type is so deep as compared with the second layer bit line type, and the distance between via sections of the positive/negative bit lines 352, 353 and a via section of the VDD power supply interconnection 354 is so close that there exists a demerit that the parasitic capacitance of the via section of bit lines 352, 353 is increased. Further, as can be seen when comparing FIG. 25 with FIG. 27, since the number of signals transmitted from the lower layer to the upper layer of the third layer bit line type are larger than that of the second layer bit line type, the number of via sections to be used increases, and thereby it may become disadvantageous in yield. However, in the case of the third layer bit line type, the positive/negative bit lines 352, 353 are disposed between the VDD power supply interconnection 354 and the VSS power supply interconnection 355, respectively, as shown in FIG. 27. Thus, both interference between the positive/negative bit lines 352, 353 in the same memory cell, and interference with the bit line in the adjacent memory cell are shielded.
The description has been made of merits such as easiness in lithographic processing and short bit line length in the horizontal memory cell in the above. However, there exists a problem also in the horizontal memory cell.
In the case of the second layer bit line type, the shape is so horizontally long that the interconnections horizontally extended are extremely close to each other. Specifically, the word line 119 and the VSS power supply interconnection 120 which are formed with the same layer as the third-layer interconnection 117 extremely, closely run in parallel for a long distance (within the whole memory area) as shown in FIG. 25, a parasitic load capacitance of the word line 119 is increased with the progress in microfabrication, and an interconnection spacing is so narrow that it becomes weak also against particles or the like caused by the process during fabrication, thereby, there is a problem that a yield drop is apt to be caused.
Further, in the case of the third layer bit line type, since the positive/negative bit lines 352, 353 are disposed between the VDD power supply interconnection 354 and the VSS power supply interconnection 355 as shown in FIG. 27, interference between bit lines in the same memory cell and also in the adjacent memory cell can be shielded; as a result, the VDD power supply interconnection 354 and the VSS power supply interconnection 355, and the positive/negative bit lines 352, 353, which are arranged in a horizontal direction, will run in parallel over a long distance. Although room is still left in breadth for a horizontal memory cell, since there exist many interconnection patterns closely with the progress in microfabrication, there is also a possibility of an increase in a parasitic load capacitance of the bit lines 352, 353, and there is a problem that a yield drop is apt to be caused due to particles.
Further, as attendant circumstances, in the latest system LSI layout, the following trends will be seen with the progress in microfabrication.
(1) Multilayered Interconnection
With the progress in microfabrication, the cross section of the interconnection is decreased in area, and the interconnection spacing is decreased in width, so that interconnection delay is increased. In order to relieve this, there have begun to increase cases where the layout has been performed in such a manner to increase the number of interconnection layers to be used to thereby make the interconnection width and the interconnection spacing wide, and accordingly, there has been a tendency that the interconnection of the system LSI has been multilayered in number.Because of the needs such as device scaling or a reduction in power dissipation of the apparatus, there has been a tendency that a supply voltage of LSIs has been reduced. However, on the other hand, since a large number of elements have been integrated on one chip, and needs for high-speed operation have also been high, there has been a tendency that a current consumption has been increased. For this reason, there have been increased the need for making the power interconnection large in width to thereby suppress a supply voltage drop, so that there has been a tendency that the number of interconnection layers to be used has been increased.
(2) Redundant Repair Technology
There has been a tendency that the number of transistors to be embedded, in particular, the memory capacity to be embedded has been increased in system LSIs. For this reason, a redundant repair technology having been used for DRAM or the like has begun to be used also for SRAM.
Taking a flow of said (1) and (2) in system LSIs which are fabricated using a micromachining process in recent years into account, it is required to further optimize the interconnection structure of the above-mentioned horizontal memory cell.